This application relates generally to electronic time measurement, and more particularly to making accurate time measurements in electronic test systems.
Many electronic products have time-critical specifications that manufacturers verify before shipping the products to customers. Manufacturers typically use automatic test equipment (ATE) to verify these specifications.
FIG. 1A illustrates a conventional ATE configuration for testing time-critical devices. As shown in FIG. 1A, an ATE system 100 is connected to a unit under test (UUT) 120 via a plurality of channels 110 attached to test points of the UUT 120. Each channel 110 includes comparators 124 and 126 that detect timing events at the UUT. The comparators generate time-sensitive signals that change in response to the timing events at the UUT. The time-sensitive signals typically follow a long path before they reach a measurement instrument, for example as a timer/counter 118. The signals pass through a first signal pathway 112 to a multiplexor 114. The multiplexor selects a pair of signals from one of the plurality of channels 110. The selected signals pass through a second signal pathway 116 and on to the timer/counter 118.
A timer/counter typically determines time intervals by measuring the delay between first and second signal edges, designated as a xe2x80x9cstartxe2x80x9d event and a xe2x80x9cstopxe2x80x9d event. The start event initiates the time measurement, and the stop event terminates the time measurement. The start and stop events are typically provided at CH1 and CH2 of the timer/counter, respectively.
FIG. 1B shows the appearance of test signals that originate at the UUT 120, at opposite points along the signal pathway between the channels 110 and the timer/counter 118. Waveform 132 depicts an ideal, rectangular test signal as it emerges from a channel 110. Waveform 124 shows the same signal as it arrives at the timer/counter 118. In contrast with the rectangular, steep-edged signal 132 at the output of the channel, the signal 134 reaching the timer/counter is slow and distorted, and its amplitude is reduced. It would be difficult for the timer/counter 118 to determine accurately the timing characteristics, for example the pulse width, of the initial signal 132 by measuring the arriving signal 134. Unlike the initial signal 132, wherein pulse width is constant, the pulse width of the arriving signal 134 varies with the threshold voltage applied. As pulse width shortens, so too does the height of the pulse at signal 134. Eventually, the pulse height becomes so short that the timer/counter cannot respond.
Another way in which the signal path between the channels 110 and the timer/counter 118 distorts test signals is by differentially delaying rising and falling edges. For example, if the signal path delays falling edges more than it delays rising edges, the signal path will erroneously lengthen positive pulse widths and shorten negative pulse widths. These errors further add to the difficulties of measuring time intervals using the configuration of FIG. 1A.
Measuring high-speed events at the UUT would be simplest if the signal pathway between the UUT and the timer/counter could maintain high bandwidth. Unfortunately, however, maintaining high bandwidth proves to be expensive, particularly if the number of channels 110 is large. As ATE systems commonly include hundreds or even thousands of channels 110, providing high bandwidth between each channel 110 and the timer/counter would excessively raise system cost. Consequently, ATE manufacturers have sought alternatives for measuring high-speed eventsin test systems having low-bandwidth paths.
One alternative to providing high-bandwidth paths would be to include one complete timer/counter within each channel. As timer/counters themselves tend to be expensive, however, it is not feasible to include one timer/counter per channel as part of a reasonably priced ATE system.
Another alternative to providing high bandwidth paths is shown in FIG. 2A. According to FIG. 2A, a tester includes channels 210 that are identical to the channels 110 of FIG. 1A, except that each channel 210 includes a pair of frequency dividers 212 and 214. The frequency dividers 212 and 214 are respectively connected in series with the comparators 124 and 126. As shown in FIG. 2B, the signal 252 at the output of each frequency divider 212, 214 has a period eight times longer than the period of the signal 250 at its input. The substantially longer period of the output signal 252 means that the signal 254 arriving at the timer/counter has more time to settle and thus can be measured more accurately. The arrangement of FIG. 2A thus enables the timer/counter to measure accurately the frequency of test signals from the UUT, even if the bandwidth of the test signals exceeds the bandwidth of the signal path.
Although the configuration of FIG. 2A marks a significant improvement over the configuration of FIG. 1A, it provides limited functionality. Because this technique sends only frequency-divided signals to the timer/counter, the timer/counter cannot measure time intervals between successive edges of an input signal. Nor can the timer/counter measure time intervals from falling edges, or between edges of different slope. Similarly, the timer/counter cannot directly measure pulse widths or single-shot periods using this technique.
With the foregoing background in mind, it is an object of the invention accurately and easily to measure time intervals between successive edges of high frequency signals.
It is another object of the invention to measure high-frequency time intervals using a relatively low-bandwidth transmission path.
To achieve the foregoing objects and other objectives and advantages, a timing circuit conveys timing relationships of UUT signals to a measurement instrument over a bandwidth-limited pathway. The timing circuit has first and second input nodes, for receiving at least one input signal from the UUT, and first and second output nodes, for connecting to the measurement instrument. The timing circuit includes a frequency divider that has an input coupled to the first input node and an output coupled to the first output node. The timing circuit also includes a clocked memory device that has a first input coupled to the output of the frequency divider and a second input coupled the second input node. The clocked memory device also has an output coupled to the second output node of the timing circuit.
In accordance with another aspect of the invention, a pre-conditioner conveys timing relationships of UUT signals to a measurement instrument. The pre-conditioner has first and second input nodes, for receiving at least one input signal from the UUT, and first and second output nodes, for respectively providing output signals to the measurement instrument. The pre-conditioner is divided into first and second circuit branches. The first circuit branch includes a first frequency divider having an input coupled to the first input node and an output coupled to the first output node. The second circuit branch includes a second frequency divider having an input coupled to the second input node and an output selectably coupled to the second output node. The pre-conditioner further includes a clocked memory device. The clocked memory device has a first input coupled to the output of one of the first and second frequency dividers and a second input coupled to the input of the second frequency divider. The clocked memory device also has an output selectably coupled the second output node.
In accordance with yet another aspect of the invention, a tester for determining whether a UUT is operating properly includes a plurality of channels connectable to the UUT and each including at least one voltage comparator. The tester includes a measurement instrument for measuring timing characteristics of the UUT and a signal pathway for conveying timing signals from the plurality of channels to the measurement instrument. Each of the plurality of channels further includes a pre-conditioner for conveying timing signals between the at least one comparator and the measurement instrument via the signal pathway. The characteristics of the pre-conditioner are set forth in the preceding paragraph.
In accordance with still another aspect of the invention, a method is disclosed for accurately measuring time intervals between first and second timing events at a UUT over a bandwidth-limited pathway. The method includes dividing the frequency of the first timing events to generate a first frequency-divided signal. The edges of the first frequency-divided signal are coincident with alternate first timing events. The method further includes generating a second frequency-divided signal having edges coincident with alternate second timing events. The second frequency-divided signal changes state at most once for each change of state of the first frequency-divided signal, and only after the first frequency-divided signal changes state. In accordance with this aspect of the invention, the first and second frequency-divided signals are conveyed to a measurement instrument. The measurement instrument determines the time interval between the first and second timing events by measuring the time interval between the first and second frequency-divided signals.
Additional objects, advantages and novel features of the invention will become apparent from a consideration of the ensuing description and drawings.